NVIDIA quietly executed one of the most aggressive cadence accelerations in semiconductor history between 2022 and 2026. The product cycle went from 2 years (Volta 2017 → Turing 2018 with a derivative gap, Ampere 2020, Hopper 2022) to annual with mid-cycle refreshes. Hopper H100 in 2022. Blackwell B200/GB200 in 2024. B300/GB300 mid-cycle in mid-2025. Rubin late 2026. Rubin Ultra 2027. Feynman 2028.
Each cadence step is roughly 2-3× FLOPs, a new memory generation (HBM3 → HBM3E → HBM4), and a new packaging tier (CoWoS-S → CoWoS-L → CoWoS-XL or successor). The market is pricing the cadence holding through 2027-2028. If it does, the revenue and margin story compounds. If a single node slips a quarter or yields disappoint, the multiple compresses fast. This article is what each milestone actually is, what supplier dependencies sit under it, and where the risk concentration lives.
The TL;DR. The annual cadence is sustainable only if (1) TSMC's N4P / N3 / N2 nodes ramp on schedule, (2) HBM3E / HBM4 / HBM4E supply ramps in lockstep, (3) CoWoS packaging capacity doubles every 12-18 months, and (4) software/firmware development absorbs the new architecture in time for hyperscaler validation cycles. Any single gap stretches the cadence. Two gaps simultaneously and the cadence breaks. Nothing in the public disclosure suggests either has happened yet, but the surface area of risk is large.
The cadence as actually executed
Hopper H100 - shipped early 2022. Process: TSMC N4. HBM: HBM3. ~80 GB memory, ~3.4 TB/s bandwidth, ~1979 TFLOPs FP16. The product that established the AI-data-center category. NVIDIA shipped roughly 500K H100s in 2023 and 2M+ in 2024 at the peak.
Hopper H200 - shipped late 2023. Mid-cycle refresh of H100 with HBM3E memory upgrade. Same N4 die, ~141 GB HBM3E, ~4.8 TB/s. Filled the gap until Blackwell.
Blackwell B200 / GB200 - shipped Q4 2024. Process: TSMC N4P. HBM: 8 stacks of HBM3E per B200, 16 per GB200 (which packages two B200 dies + a Grace CPU on the same module). ~192 GB memory per B200, ~8 TB/s bandwidth, ~10 PFLOPs FP4 (the new low-precision format Blackwell introduced). The ramp absorbed all of TSMC's N4P + CoWoS-L + Korean HBM3E output for 18 months.
Blackwell B300 / GB300 - mid-cycle refresh, shipped mid-2025. Same N4P die, 12-stack HBM3E (~288 GB), ~10-12 TB/s bandwidth. Mid-cycle because Rubin's N3 process slipped slightly and NVIDIA filled the gap with a memory-uplift refresh on the existing die.
Rubin / GR200 - ships late 2026 (target). Process: TSMC N3. HBM: HBM4 (announced spec, 1.5-2× HBM3E bandwidth). New CoWoS-XL packaging tier. Expected ~2.5-3× B200 throughput on training workloads. Grace CPU upgrade to Grace 2 expected for GR200 superchips.
Rubin Ultra - 2027 (target). Mid-cycle refresh of Rubin with HBM4E memory uplift and yield-improved N3 die.
Feynman - 2028 (target). Process: TSMC N2 or N3-derivative. HBM: HBM4E or HBM5. Architecture details not publicly disclosed; pre-announced as "next major architecture after Rubin."
The cadence pattern: major architecture every two years, mid-cycle refresh every year between. The 2-year architecture cadence is similar to the historical pace; the yearly product cadence (major + refresh stacked) is new and aggressive.
Why the cadence matters for the financial model
NVIDIA's bull-case earnings model has three implicit assumptions:
1. Each generation expands the addressable workload class. Hopper enabled GPT-3-class training at meaningful scale; Blackwell enabled Llama-3-405B and GPT-4-class with reasonable training times; Rubin enables 1T-parameter+ models and frontier training-runs that consume 50,000+ GPU clusters. As long as each cadence step opens up a new tier of model that wasn't economically feasible before, demand expands faster than supply.
2. ASP holds (or grows) per generation. Hopper H100 launched at ~$30K ASP. Blackwell B200 launched at ~$40K. Rubin is expected to launch at ~$50K+. The chip is getting more expensive per unit even as the FLOPs/dollar improves materially - because each generation enables workloads that were impossible at the prior generation's economics. Customers pay for the new tier of capability, not for the marginal FLOPs.
3. Volume ramp accelerates. Hopper sold ~3M units across 2023-2024. Blackwell is on track to sell 5-7M units across 2025-2026. Rubin is projected for 8-12M units across 2026-2028. Each generation has a larger TAM because each generation has more deployed AI workloads to serve.
The compounding effect: ASP × Volume × Annual cadence = the revenue ramp the market is pricing. If any of the three legs weakens - ASP gets pressured by AMD or custom silicon, volume slips due to HBM supply or customer in-housing, or cadence slips due to fab or packaging issues - the model derates.
Where the cadence risk actually lives
Three nodes in the supply chain that gate the roadmap:
Node 1 - TSMC process. N4P (Blackwell), N3 (Rubin), N2 (Feynman). TSMC has executed N4/N4P/N3 on schedule. N2 (planned for 2028 mass production) is the first node using gate-all-around (GAA) transistors at TSMC and the first node where the public schedule shows some buffer. If N2 slips a quarter or yields are worse than guidance, Feynman compresses or shifts to an N3-derivative.
Node 2 - HBM. HBM3E supply ramp at SK Hynix/Samsung/Micron through 2026. HBM4 qualification 2026-2027. HBM4E development for 2027-2028. The Korean memory oligopoly controls this lane; capex visibility is annual. If HBM4 qualification slips at the high-spec tier (which happened with HBM3E at Samsung), the Rubin ramp's memory configuration may be downgraded or staged. See the HBM bottleneck analysis for the supply-side detail.
Node 3 - CoWoS packaging. TSMC's CoWoS capacity has been the binding constraint on Blackwell at multiple points in 2024-2025. CoWoS-L for Blackwell, CoWoS-XL for Rubin. Each tier requires new fab equipment, new process qualification, and 18+ month lead times. TSMC is investing heavily but the capacity ramp is lumpy - a delayed equipment delivery (Applied Materials, Tokyo Electron, ASML EUV scanners for the interposer layers) ripples into NVIDIA's product launch dates.
The risk concentration is vertical - NVIDIA is dependent on TSMC for process, SK Hynix/Samsung/Micron for memory, and TSMC again for advanced packaging. There is no second-source for any of the three at the leading edge. A single supplier issue at any of the three nodes delays the cadence.
What's already happened (and what hasn't)
The cadence-execution record so far:
Hopper H100 → on time, 2022. Met schedule.
Hopper H200 → on time, late 2023. Met schedule. Memory upgrade as expected.
Blackwell B200 → ~1 quarter slip. Originally targeted Q3 2024, slipped to Q4 2024 on a packaging-related issue that NVIDIA disclosed in earnings. Hyperscalers absorbed the slip.
Blackwell B300 → on time, mid-2025. Mid-cycle refresh shipped on the announced window.
Rubin → expected Q4 2026. Currently tracking the announced window per management commentary. No public disclosure of slippage.
The pattern: small slippages get absorbed without breaking the cadence, but a >1 quarter slip on a major generation would. The B200 quarter-slip didn't move the stock materially because the supply was already sold and the demand bucket simply shifted forward. A Rubin half-year slip would move the stock - because the implied 2027 revenue model assumes Rubin volume contributing meaningfully through that year.
The competing read - is the cadence sustainable?
Two counter-positions worth taking seriously:
Counter-position 1: The cadence is unsustainable. Annual major architectures with mid-cycle refreshes is faster than any other complex-SoC vendor has sustained. Intel's tick-tock cadence broke at the 10nm node. AMD's annual cadence on the consumer side has had multiple delays. NVIDIA is asking for more than tick-tock - they're shipping a new architecture every year with new memory and new packaging. Something will break eventually.
Counter-position 2: The cadence is sustained but ASP can't follow. Even if NVIDIA ships every generation on time, the diminishing-returns curve on FLOPs/dollar improvement means customers may not pay the next ASP step-up. If Rubin ships at $50K and Feynman wants to launch at $70K, the customer math (return on a $70K accelerator vs the $50K predecessor) may not pencil unless workloads are still expanding. This is the deeper bear case - not that NVIDIA fails to execute the roadmap, but that the market for accelerators reaches a price ceiling.
The current bull-case price probably weighs Counter-1 (cadence risk) and discounts Counter-2 (ASP-ceiling risk) too heavily. Trader pushback that focuses on AMD or HBM tends to miss that the real multi-year vulnerability is whether AI workloads keep expanding fast enough to absorb yet another generation of more-expensive silicon.
The trade-relevant frame. The cadence is priced as a base case. The two risk vectors are cadence slip (delays Rubin / Feynman by quarters) and ASP-ceiling (customers don't pay the next step-up). The first is a 1-2-year multiple compression; the second is a structural growth-rate reset. Both are real. Neither is current. The mid-2026 thesis is that the cadence holds through Rubin and the ASP-ceiling question gets visible answers in late 2027 when Rubin Ultra and Feynman launches frame the next generation's pricing. Trade the supply side (HBM) and the demand side (customer concentration) separately for cleaner exposure.
Three things to watch for cadence breakage
1. NVIDIA earnings-call commentary on packaging or memory supply. If management starts hedging Rubin shipment timing more heavily than they did with B200, that's the leading indicator. "Working closely with our packaging partners" → "on track" → "extending the ramp" → "deferred" is the language degradation cycle.
2. TSMC's CoWoS-XL capacity disclosures. TSMC discloses advanced-packaging capacity quarterly without naming customers. If CoWoS-XL ramp slips on TSMC's public capacity table, NVIDIA's Rubin volume implicitly compresses.
3. SK Hynix HBM4 qualification announcements. Samsung and SK Hynix qualifying HBM4 at NVIDIA for the high-spec Rubin product is the gating event. Watch Korean press for ramp progress through 2026. If HBM4 qualification slips past Q3 2026, Rubin's launch HBM configuration may be downgraded or staged.
Bottom line
NVIDIA's annual product cadence - Blackwell to B300 to Rubin to Rubin Ultra to Feynman - is the most aggressive execution program in semiconductors and it's the structural driver of the implicit revenue model the market is pricing. The cadence has held through 2025; it gets harder from here. The risk vectors are concentrated in three external suppliers (TSMC for process, the HBM oligopoly for memory, TSMC for packaging) and any single slip at any of those nodes delays the cadence.
For traders, the cadence is "priced as base case." That means the upside from execution is limited and the downside from any meaningful slip is large. The supply-side trade (HBM bottleneck) and the demand-side trade (customer concentration) are cleaner exposures to the cadence variable than NVDA stock itself, because they isolate the specific risk legs without the cadence-execution residual.
NVDA dashboard on QuantAbundance - thesis panel with current marks.
The CUDA moat - the software defense that the cadence speed feeds.
NVIDIA's HBM bottleneck - the supply-chain dependency that gates each cadence step.
Custom ASIC threat assessment - the demand-side competitor whose own cadence runs parallel to NVDA's.
To trade $NVDA from a US-retail or LLC account, see /stack/ibkr. Bubble shifts and rule-based alerts on $NVDA across each cadence step are part of /pro.
