DDR5 memory interfaces represent a significant step change in PCB manufacturing requirements. Operating at 4800-6400 MT/s with 1.1V supply voltage, DDR5 demands fabrication tolerances that standard processes simply cannot deliver. This guide covers the manufacturing perspective — what to specify, what your fab controls, and where the common failure points hide.
Key Changes from DDR4 to DDR5
DDR5 introduces dual-channel DIMM architecture, reduced operating voltage (1.1V vs 1.2V), on-DIMM power management, and decision feedback equalization. From a PCB standpoint, these translate to tighter impedance requirements, more routing layers, and stricter material specifications.
The reduced voltage means every millivolt of noise consumes a larger fraction of signal swing. Manufacturing tolerances acceptable for DDR4 become failure-inducing for DDR5.
Impedance Requirements
DDR5 signals fall into three groups:
- Data byte lanes (DQ, DQS, DM): 40 ohm single-ended, matched within 5 mils
- Address/Command: 40 ohm SE, matched within 50-100 mils to clock
- Clock (CK): 80-100 ohm differential, internal pair match within 2 mils
Achieving 40 ohm at +/-5% tolerance requires trace width control to +/-0.3 mils — significantly tighter than the +/-0.5-0.7 mil typical in standard fabrication.
Material Selection
Standard FR-4 (Df > 0.015) fails at DDR5 frequencies. The practical tiers:
Mid-loss (short channels < 3 inches, DDR5-4800):
- Panasonic Megtron 4 (Df ~0.005)
- Isola FR408HR (Df ~0.009)
- TUC TU-872 SLK (Df ~0.006)
- Cost: 1.5-2.5x standard FR-4
Low-loss (long channels, DDR5-5600+):
- Panasonic Megtron 6 (Df ~0.002)
- Isola I-Speed (Df ~0.005)
- Isola I-Tera MT40 (Df ~0.003)
- Cost: 3-4x standard FR-4
Copper foil matters too. HVLP or RTF copper (Rz < 2um) reduces skin-effect loss by 0.2-0.4 dB/inch at 10 GHz compared to standard ED copper.
Stackup Fundamentals
Every DDR5 signal layer must be immediately adjacent to a continuous ground reference plane. No exceptions.
8-layer example: Signals on L1, L3, L6, L8 with ground on L2, L4, L5, L7. Signal-to-reference dielectric: 3.5-4.5 mils.
12-layer example: Signals on L1, L3, L5, L8, L10, L12 with ground on L2, L4, L6, L7, L9, L11. The GND-GND pair at L6/L7 provides excellent high-frequency decoupling.
Via Stub Management
Via stubs create quarter-wave resonances that notch the channel response. A 40-mil stub resonates at ~18 GHz; a 60-mil stub at ~12 GHz. Both fall within DDR5 signal bandwidth.
Maximum acceptable stub for DDR5: 10 mils.
Options:
- Back-drilling: +10-20% cost, depth tolerance +/-4-6 mils
- Blind/buried vias: +20-35% cost, deterministic stub elimination
- Microvias: Best for BGA breakout, 0.1-0.15mm laser-drilled
Cost Impact
DDR5-grade boards typically cost 30-60% more than equivalent standard fabrication:
- Material premium: 2-4x for laminates
- Process premium: 15-30% for tighter etch, 100% AOI, back-drilling
- Yield impact: First-pass yield drops from 95%+ to 85-90% at +/-5% impedance
What to Specify in Your Fab Drawing
- Impedance targets with tolerance (e.g., "40 ohm +/-5% SE, 100 ohm +/-5% differential")
- Specific approved materials (not just "FR-4")
- Maximum via stub length (< 10 mil, with back-drill callout)
- Stackup with dielectric dimensions and copper weights
- Impedance coupon requirements per IPC-TM-650
Common DFM Issues We See
From our production floor, the most frequent DDR5 failures:
- No material callout — fab uses standard FR-4, signals fail
- Missing impedance tolerance — fab assumes +/-10%, too loose for DDR5
- No back-drill specification — via stubs degrade high-frequency signals
- Reference plane voids — discontinuities under signal traces cause impedance spikes
- Insufficient byte-lane spacing — crosstalk between adjacent data groups
Originally published at AtlasPCB Engineering Blog. AtlasPCB specializes in controlled impedance PCB fabrication for high-speed memory interfaces, RF systems, and HDI designs.
