Over the past 18 months, the underlying rules of PCB design have been quietly rewritten.
No press releases. No industry announcements. But the "new hidden requirements" buried in datasheets are forcing hardware engineers to rethink their designs and validation teams to scrap three versions of test plans.
This isn't a macro forecast from an industry trends report. It's what's happening right now on every production-level project. As signal rates push into 112G PAM4, package sizes approach physical limits, and AI begins to seep into design flows, classic design methodologies are being forcibly patched.
Here are six of the most important changes that every hardware engineer needs to understand.
1. Copper Foil Roughness: The Hidden Loss Killer
Old thinking: Copper just needs to meet thickness specs.
Reality: Copper foil surface roughness (Rz value) has become a critical parameter determining high-speed signal integrity. At 28GHz and above, different plating processes produce Rz values ranging from 0.8 to 4.0μm — a 5x difference that translates into up to 0.5dB/inch of insertion loss variation.
More critically, low-loss laminates (like Megtron 7, TU-872 SLK) only deliver their specified loss values when paired with compatible copper foil treatments. The wrong foil treatment negates the investment in expensive high-end materials.
Design impact: Leading OEMs are now specifying copper foil roughness parameters directly on PCB fabrication drawings — e.g., "Rz ≤ 2.0μm on signal layers, HVLP treatment" — not just copper thickness. For ultra-high-speed designs like 112G PAM4, HVLP or HVLP2 copper foil with Rz values below 2μm is essential to meet insertion loss budgets at the 32GHz Nyquist frequency.
2. Vias Are No Longer Just Vias
Old thinking: Vias are simply tunnels connecting layers.
Reality: Vias have become one of the primary bottlenecks limiting high-speed signal integrity. In PCIe 6.0 (64 GT/s PAM4) and PCIe 7.0 designs, the requirements for via stub length, stack geometry, and breakout routing precision are being pushed to their limits.
For PCIe 7.0, production-stage via stub lengths are specified at 5±3mil, with stack geometry of 8/14/24mil. Advanced sample stages have already achieved 1±1mil stub lengths and 6/12/20mil stack dimensions. This progress is driven by breakthroughs in advanced back-drilling and high-precision registration technology.
Design impact: Back-drilling is no longer optional — it's a standard requirement for high-speed designs. Stub control has moved from "as short as possible" to "accurate to ±1mil," requiring PCB manufacturers to have much more precise depth control. Five-point fiducial marking, combined with AI-assisted recognition, is becoming standard practice to improve layer-to-layer registration.
3. Capacitor Aging Curves Are Now Selection Criteria
Old thinking: Capacitor selection is about capacitance, voltage rating, and package size.
Reality: Automotive-grade MLCCs now have a hidden requirement: capacitance drift after 10 years of aging at 125°C must be controlled within ≤±3.2%. Two brands with the same value and same package can have dramatically different long-term reliability profiles.
Design impact: Selection now requires looking beyond the datasheet's initial specs. You need to examine the supplier's aging curves and temperature characteristics. For automotive electronics, industrial controls, and other products requiring 10+ year lifetimes, long-term capacitance stability is becoming the deciding factor in reliability.
4. Resistor Impedance Phase at High Frequency
Old thinking: Resistor selection is about resistance tolerance and power rating.
Reality: In high-speed ADC front-ends and RF circuits, the impedance phase angle deviation of resistors in the 100kHz–1GHz band is now being specified at <±1.8°. At high frequencies, parasitic inductance and capacitance change the resistor's impedance characteristics, directly impacting signal integrity.
Design impact: For high-frequency circuits, DC resistance accuracy alone is insufficient. You need to examine frequency response characteristics and prioritize thin-film resistors with lower parasitics over general-purpose thick-film alternatives.
5. PCB Laminate: Dk=3.65 No Longer Applies
Old thinking: FR-4 has a fixed dielectric constant (Dk).
Reality: In 10Gbps SerDes designs, using a fixed Dk value (like 3.65) for impedance calculations without a frequency-dependent Dk model can introduce up to 42% error in eye opening. Dielectric constant actually varies with frequency — in high-speed designs, ignoring this leads to impedance calculations that significantly deviate from real-world values.
Design impact: High-speed designs require frequency-dependent Dk/Df data from laminate suppliers, and simulations must use this data. For SerDes channels running at 112G and above, copper roughness models (Hammerstad-Jensen or Huray) must also be included to account for conductor loss.
6. AI Is Changing the Design Tool Landscape
Old thinking: EDA tools are for schematics and routing.
Reality: AI is moving from "assisted routing" to "full-flow design closure." At the 2026 Design Automation Conference, Xpeedic and Lenovo jointly demonstrated an EDA Agent achieving a closed-loop AI design flow spanning PCB design to simulation. The AI agent now covers four key steps: library creation, placement, DRC, and simulation optimization.
In real-world validation:
- Automated library creation for schematic symbols and PCB footprints improved efficiency by 50%+
- Full-link SERDES optimization achieved 80%+ improvement in simulation efficiency
Keysight also launched PathWave Signal Integrity AI Suite in 2026, using machine learning to predict signal integrity failures before physical prototyping — reducing compliance test cycles by up to 60%.
Design impact: Tools are changing, but engineer judgment matters more than ever. AI can automate checks, accelerate iterations, and predict failures — but it can't make design trade-offs. Understanding the physics behind the tools is still more important than trusting the tool's "authority."
What This Means for Hardware Engineers
As process nodes approach atomic scales, signals enter the millimeter-wave band, and system integration moves toward chiplet-based heterogeneous architectures, classical design methods are being forced to evolve.
For hardware engineers, this means:
- Component selection now requires looking beyond the datasheet to actual performance under real-world conditions
- Simulations need to incorporate models that are closer to physical reality — frequency-dependent Dk, copper roughness, temperature coefficients
- PCB design is shifting from "making it work" to a battle against physical limits
Engineers and manufacturers who understand these "new hidden rules" early will have a decisive advantage in the next wave of competition.
If You're Facing High-Speed PCB Design Challenges
AnyPCBA has over a decade of experience in PCB manufacturing, supporting 2-64 layers including HDI, rigid-flex, and high-frequency hybrid technologies. Our engineering team provides DFM/DFA design reviews during the design phase — helping identify potential risks in material selection, via structures, and impedance control. In an era of high-frequency, high-density designs, early detection and resolution of issues is more critical than ever.
👉 If you have high-speed PCB design or manufacturing requirements, feel free to reach out through our website.
