We have been building RISC-V cores, IP, VIP, accelerators and SoC reference designs.
For WZ-HFT, we pushed those components through a latency-sensitive trading pipeline.
A warm market-data event crosses WZ-HFT from the final received byte after CDC to the first generated order byte in 12 clock cycles.
On the first prototype:
50 MHz → 20 ns/cycle → 240 ns
Four first-valid events took 20 cycles because the initial imbalance calculation adds a fixed eight-cycle dependency.
So the latency classes are deterministic:
Warm path: 12 cycles First-valid path: 20 cycles
The important result is the pipeline depth.
At 300 MHz, the same 12-cycle path corresponds to 40 ns. At 400 MHz, it corresponds to 30 ns.
Those frequencies still need implementation and timing closure, but the cycle depth is already defined by the architecture.
The pipeline combines:
market-data ingest → parsing → order book → feature generation → MLP decision → risk → order egress
This experiment also showed exactly where the CPU should leave the critical path and where the remaining latency dependency sits.
Full engineering note: https://wiowiz.com/wz-hft-12-cycles.html
