The sm_120 shared-memory cliff: why FP8 KV cache crashes vLLM on workstation Blackwell

If you run vLLM with --kv-cache-dtype fp8 on a DeepSeek-family (MLA) model and your GPU is a GB10, an RTX PRO 6000, or any workstation or consumer Blackwell card, there is a decent chance the engine dies on startup with:

triton.runtime.errors.OutOfResources: out of resource: shared memory,
Required: 102400, Hardware limit: 101376. Reducing block sizes or `num_stages` may help.

We hit this, measured exactly where the 1,024 missing bytes come from, and posted the measurements on the upstream issue (vllm-project/vllm#53748). This post is the diagnostic method, because it applies to any Triton kernel on this hardware class, not just this one bug.

The hardware fact underneath

Datacenter Blackwell parts advertise a larger per-block shared-memory budget than the workstation and consumer silicon. On an RTX PRO 6000 Blackwell (sm_120), torch.cuda.get_device_properties reports:

GB10 (DGX Spark) reports the same 101,376-byte per-block opt-in limit. So a kernel tuned to fit 102,400 bytes fits the SM but not the block, and the whole workstation Blackwell class fails together. If your kernel config was validated on H100 or B200 numbers, this is the cliff you fall off when someone runs it on a desk machine.

The five-minute probe

Do not debug this inside the serving engine. Launch the suspect kernel directly with the exact tile configuration the engine would pin, sweep num_stages, and read the compiled kernel's shared-memory size. For vLLM's MLA decode kernel (_fwd_grouped_kernel_stage1) with the DeepSeek tile shape (BLOCK_DMODEL=512, BLOCK_DPE=64, BLOCK_DV=512, BLOCK_N=32, BLOCK_H=16, num_warps=4):

The table says everything. With bf16 KV, an extra pipeline stage costs about 4 KB and even four stages sit far under the limit. With fp8 KV, a stage costs about 18 KB, and stage two lands on 102,400 bytes: exactly the full per-SM budget, and 1,024 bytes over the per-block cap. The crash is specific to the fp8 KV path; MLA with bf16 KV is fine at these tile sizes.

The probe is ordinary Triton: import the kernel function, build dummy tensors for the tile shape, launch once per (dtype, num_stages) combination, and catch OutOfResources. The compiled size is on kernel.metadata after a successful launch. No server, no model download, under a minute per configuration.

Reproducing end to end

DeepSeek-V2-Lite-Chat is the smallest convenient MLA model with the same Lk=576 head layout (512 latent plus 64 rope):

vllm serve deepseek-ai/DeepSeek-V2-Lite-Chat --trust-remote-code \
  --enforce-eager --kv-cache-dtype fp8 --max-model-len 4096

On sm_120 the backend selector reports TRITON_MLA as the only MLA decode option, so there is no fallback path: the engine dies during the startup dummy run (vLLM 0.27.1, torch 2.13.0+cu130, triton 3.7.1, CUDA 13.1).

What a durable fix looks like

The upstream patch direction pins num_stages=1 for MLA kernels on non-HIP devices, which makes the server start and generate correctly (we validated greedy output on sm_120 after applying it). But the sweep shows why a blanket is_mla condition costs something: bf16 KV at two stages fits comfortably (63,488 < 101,376), and the second stage exists for throughput. The robust rule is to compute the tile's actual shared-memory requirement and compare it against shared_memory_per_block_optin for the device you are actually on. That handles GB10, RTX PRO 6000, and whatever ships next, without a special case per chip.

The general lesson for anyone shipping Triton kernels: your shared-memory budget is a per-block, per-device property, not a compile-time constant, and the workstation cards your users actually own report smaller numbers than the datacenter parts your CI runs on. Probe first; it takes five minutes.

This came out of inference engineering work on Blackwell workstations. The benchmark that surrounds it, with raw data and reproduction scripts, is here: https://conatus.jahn.ai/ai-engineering/sample-report