72% of first-time PCB submissions require at least one design revision. Here's how to run a proper DFM (Design for Manufacturability) check and avoid being in that majority.
Quick Reference: Critical DFM Parameters
| DFM Parameter | Standard PCB | HDI PCB | Failure Mode |
|---|---|---|---|
| Min trace width | 4 mil (100um) | 3 mil (75um) | Open circuit |
| Min space | 4 mil (100um) | 3 mil (75um) | Short circuit |
| Min annular ring | 4 mil (100um) | 2 mil (50um) | Via breakout |
| Min drill (mech.) | 0.2mm | 0.15mm | Drill breakage |
| Min drill (laser) | N/A | 0.075mm | Incomplete ablation |
| Drill-to-copper | 8 mil (200um) | 5 mil (125um) | Short to copper |
| Solder mask dam | 3 mil (75um) | 3 mil (75um) | Solder bridging |
| Copper-to-edge | 10 mil (250um) | 8 mil (200um) | Copper exposure |
If your design passes all parameters above against your fabricator's specs, you've eliminated the majority of manufacturing risk.
What a Professional DFM Check Actually Verifies
Most engineers think of DFM as simply running a DRC in their EDA tool. That catches the obvious — spacing violations, unrouted nets — but misses manufacturing-specific constraints that cause real production failures.
Layer-by-Layer Copper Analysis
Acid traps (acute-angle copper junctions below 90 degrees) create pockets where etchant cannot flow, leaving copper residue that causes shorts. In our DFM review process, we flag approximately 8-12 acid traps per average 8-layer board. Most are in ground plane reliefs where the auto-router created suboptimal thermal connections.
Drill File Integrity
Common issues we catch daily: overlapping drill hits (creating slots instead of holes), drill sizes not matching standard tooling, and drill hits placed too close to board edge.
One particularly insidious issue: non-plated holes placed too close to copper features. Unlike plated through-holes, NPTH holes are bare drilled — any copper within 10 mil of the hole edge risks burr-induced shorting.
The Top 5 DFM Failures We See Every Week
Based on production data from our facility (2000+ unique designs per month):
1. Annular Ring Breakout (34% of DFM flags)
A 0.3mm drill with 0.5mm pad, with typical +/-2 mil registration tolerance, drops effective annular ring from 4 mil nominal to 2 mil worst-case.
Fix: Increase via pad size by 2 mil. For 0.3mm vias, use minimum 0.55mm pad (5 mil annular ring nominal).
2. Trace/Space Violations in BGA Breakout (28%)
A 0.5mm pitch BGA with dogbone vias requires 3/3 mil trace/space — putting the design at HDI capability limits. Standard fab (4/4 mil) cannot produce this.
Fix: Confirm fabricator supports 3/3 mil before routing. Alternatively, use via-in-pad or higher layer count.
3. Missing Solder Mask Dams (18%)
Fine-pitch QFP or connector pads spaced such that mask dam falls below 3 mil minimum. Fabricator must either eliminate the dam (risking solder bridges) or reject the design.
4. Impedance Stackup Incompatibility (12%)
Engineers specify impedance requirements but design trace widths based on theoretical stackups that don't match available laminate thicknesses. When the fabricator runs simulation against real material data, required trace width may differ by 1-2 mil.
Fix: Request your fabricator's standard stackup options before layout. Use their actual Dk values for impedance calculations.
5. Copper Balance and Warp Risk (8%)
Boards with >30% copper percentage difference between top/bottom warp during lamination and reflow.
Running Your Own DFM Check
Altium Designer
Set design rules to match fabricator capabilities:
- Routing > Width: fabricator min trace
- Routing > Clearance: fabricator min space
- Manufacturing > MinimumAnnularRing: match fab spec
- Manufacturing > MinimumSolderMaskSliver: 3 mil minimum
KiCad 8.x
Configure custom rules file (.kicad_dru) with fabricator-specific constraints. Focus on via_annular_ring and silk_clearance rules.
Cadence Allegro
Set Physical constraints under Manufacturing category: Minimum Etch, Minimum Space, Minimum Pad-to-Pad. Run "Design Audit" before Gerber output.
Pre-Submission Checklist
Before sending Gerber files to any fabricator:
| Check | How to Verify | Pass Criteria |
|---|---|---|
| File completeness | Open in viewer, count layers | All layers + drill file present |
| Board outline | Verify closed contour | Single closed polygon |
| Drill format | Confirm Excellon 2 | Coordinates match copper |
| Net connectivity | Netlist vs. Gerber compare | Zero opens/shorts |
| Layer stack order | Document in fab drawing | Unambiguous naming |
| Impedance notes | In fab drawing | Target Z, tolerance, ref layers |
A complete, unambiguous file package is the single most effective way to avoid DFM-related delays. We receive ~15% of orders with ambiguous layer assignments or missing drill files — each adding 12-24 hours of clarification time.
When DFM Is Non-Negotiable
- Any board going to production volume (yield loss at scale is expensive)
- HDI PCB designs with features below 4/4 mil
- Impedance-controlled designs
- Regulated industries (medical, automotive, aerospace)
- 8+ layer boards (registration affects annular rings)
- Flex and rigid-flex designs
Originally published on the AtlasPCB Engineering Blog. Every order at AtlasPCB includes DFM review with engineering recommendations — upload your Gerber files to get started.
