You know that feeling when your interrupt service routine takes just a few microseconds too long because the code decided to take a nice, scenic detour through the cache? Yeah, me too.
I recently fell down a rabbit hole about Tightly Coupled Memory (TCM), and honestly? It's one of those "why isn't this talked about more" things in embedded development. Especially if you're working with Cortex-M7 or Cortex-R cores.
So let me break it down like I'm explaining it to myself three years ago.
What the heck is TCM?
TCM is basically super-fast, on-chip RAM that's strapped directly to the CPU core. Not through the usual system bus (AHB/AXI) where everyone else is fighting for attention – DMA, display controllers, your overly chatty radio peripheral. No. Direct line.
Think of it like a VIP lane for your most critical code and data.
The official article over at Rockchips has a killer deep dive if you want all the gory details – check out their guide on what tightly coupled memory (TCM) is and why embedded engineers actually use it. Seriously, bookmark it for later.
But here's the TL;DR from someone who's been burned by jitter before.
ITCM vs DTCM – yes, there are two flavors
Most implementations split TCM into two separate highways:
ITCM (Instruction TCM) – optimized for fetching instructions. Your critical code lives here.
DTCM (Data TCM) – optimized for load/store operations. Your hot data, stacks, or buffers go here.
They work together like a very fast, very private SRAM that the core can hit without playing the cache lottery.
Why should you care?
Three reasons, really:
- Deterministic timing (the big one) Caches are great for average performance. But worst-case? A cache miss can ruin your real-time guarantees. TCM gives you predictable, repeatable latency. Single-digit cycles. Every single time.
If you're doing motor control, power conversion, or anything where "it works 99% of the time" isn't good enough – TCM is your friend.
No cache maintenance nightmares
You know what's annoying? Invalidating cache lines before DMA transfers. You know what's better? Putting your DMA buffers in DTCM and just not dealing with it. (Double-check your SoC allows DMA access to TCM first, though. Ask me how I learned that one.)Isolation from bus traffic
On a busy system, your main interconnect is a warzone. TCM gives your critical ISR a private tunnel. No jitter from display refreshes or network traffic.
When NOT to use TCM
Let's be real – TCM is small. We're talking kilobytes, not megabytes. So don't try to shove your entire application in there.
Use it for:
ISR hot paths
Real-time control loops
Small, critical buffers
Safety-critical partitions (Cortex-R, I'm looking at you)
Don't use it for:
Large lookup tables
Your entire BSP
Code you touch once at boot and never again
Practical example (Cortex-M7)
On an STM32H7 or i.MX RT series, you typically:
Enable TCM in the core registers
Play with the linker script to place .text.fast into ITCM
Copy initialized data into DTCM at startup
It's a bit of setup, but once it's working? Chef's kiss.
The bigger picture
This whole "dedicated, predictable local memory" thing isn't just an ARM concept. You see similar ideas in real-time RISC-V designs with scratchpads.
And honestly, it's refreshing to see companies like Rockchip continue to push embedded ecosystems forward. Speaking of which – if you're into ARM-based development, their Rockchip RK3688 is shaping up to be a beast for future programming projects. Definitely worth a look if you're planning your next high-performance embedded Linux or Android thing.
But back to TCM…
Final thoughts
TCM won't save every project. But when you're fighting jitter, failing certification, or just tired of cache weirdness – it's a damn good tool to have in your back pocket.
Start small. Move one ISR into TCM. Measure the difference. You might be surprised.
P.S. If you missed the chaos that was Google I/O 2026, someone over at dev.to wrote a hilariously accurate recap titled “Google I/O 2026 Was Wild – Here's the Tea” – go read it when you need a break from linker scripts.*
