An universal asynchronous receiver/transmitter (UART) is a hardware feature that processes communications (i.e. timing requirements and data frames) using widely adopted asynchronous serial communication interfaces such as RS232, RS422, and RS485. UART provides a widely adopted and inexpensive way to achieve full duplex or half duplex data exchange between different devices.

Basic knowledge

Each UART controller can configure parameters independently, including baud-rate, data bit length, bit queue, stop bit quantity and parity check. All regular UART controllers will be compatible with the device that supports UART of individual manufacturer.
In UART communication, two UARTs communicate directly with each other. The transmitting UART converts parallel data from a controlling device like a CPU into serial form, transmits it in serial to the receiving UART, which then converts the serial data back into parallel data for the receiving device. Only two wires are needed to transmit data between two UARTs. Data flows from the Tx pin of the transmitting UART to the Rx pin of the receiving UART:

UARTs transmit data asynchronously, which means there is no clock signal to synchronize the output of bits from the transmitting UART to the sampling of bits by the receiving UART. Instead of a clock signal, the transmitting UART adds start and stop bits to the data packet being transferred. These bits define the beginning and end of the data packet so the receiving UART knows when to start reading the bits.

When the receiving UART detects a start bit, it starts to read the incoming bits at a specific frequency known as the baud-rate. Baud-rate is a measure of the speed of data transfer, expressed in bits per second (bps). Both UARTs must operate at about the same baud-rate. The baud-rate between the transmitting and receiving UARTs can only differ by about 10% before the timing of bits gets too far off.

Both UARTs must also must be configured to transmit and receive the same data packet structure.

How UART works

Introduction-to-UART-Data-Transmission-Diagram

The UART that is going to transmit data receives the data from a data bus. The data bus is used to send data to the UART by another device like a CPU, memory, or micro-controller. Data is transferred from the data bus to the transmitting UART in parallel form. After the transmitting UART gets the parallel data from the data bus, it adds a start bit, a parity bit, and a stop bit, creating the data packet. Next, the data packet is output serially, bit by bit at the Tx pin. The receiving UART reads the data packet bit by bit at its Rx pin. The receiving UART then converts the data back into parallel form and removes the start bit, parity bit, and stop bits. Finally, the receiving UART transfers the data packet in parallel to the data bus on the receiving end:

UART Block Diagram

The UART block diagram consists of two components namely the transmitter & receiver that is shown below. The transmitter section includes three blocks namely transmit hold register, shift register and also control logic. Likewise, the receiver section includes a receive hold register, shift register, and control logic. These two sections are commonly provided by a baud-rate-generator. This generator is used for generating the speed when the transmitter section & receiver section has to transmit or receive the data.

The hold register in the transmitter comprises the data-byte to be transmitted. The shift registers in transmitter and receiver move the bits to the right or left till a byte of data is transmitted or received. A read (or) write control logic is used for telling when to read or write.

The baud-rate-generator among the transmitter and the receiver generates the speed that ranges from 110 bps to 230400 bps. Typically, the baud rates of micro-controllers are 9600 to 115200.

Frame structure

UART transmitted data is organized into packets. Each packet contains 1 start bit, 5 to 9 data bits (depending on the UART), an optional parity bit, and 1 or 2 stop bits:

IDLE STATUS

High level. Which means there is no data transmission in current path.

START BIT

The UART data transmission line is normally held at a high voltage level when it’s not transmitting data. To start the transfer of data, the transmitting UART pulls the transmission line from high to low for one clock cycle. When the receiving UART detects the high to low voltage transition, it begins reading the bits in the data frame at the frequency of the baud rate.

DATA FRAME

The data frame contains the actual data being transferred. It can be 5 bits up to 8 bits long if a parity bit is used. If no parity bit is used, the data frame can be 9 bits long. In most cases, the data is sent with the least significant bit first.

PARITY

Parity describes the evenness or oddness of a number. The parity bit is a way for the receiving UART to tell if any data has changed during transmission. Bits can be changed by electromagnetic radiation, mismatched baud rates, or long distance data transfers. After the receiving UART reads the data frame, it counts the number of bits with a value of 1 and checks if the total is an even or odd number. If the parity bit is a 0 (even parity), the 1 bits in the data frame should total to an even number. If the parity bit is a 1 (odd parity), the 1 bits in the data frame should total to an odd number. When the parity bit matches the data, the UART knows that the transmission was free of errors. But if the parity bit is a 0, and the total is odd; or the parity bit is a 1, and the total is even, the UART knows that bits in the data frame have changed.

STOP BITS

To signal the end of the data packet, the sending UART drives the data transmission line from a low voltage to a high voltage for at least two bit durations.

Baud-rate

The frequency modulated in signal in line, expressed in bits per second (bps) or b/s. The clock signal with fixed frequency will vibrate and send one bit data signal each clock period.

It is demanded by UART communication that the both sides should be aligned in baud-rate. However, since the UART is asynchronous, that is to say there is not a clock line to connect each other. As a result, both of them will modulate one equivalent baud-rate according to internal clock theoretically. However, due to the inevitable error in HW itself, the actual baud-rate will not be aligned with theoretical value. While it is demanded that the error in baud-rate of both sides can differ only about 10%, otherwise, the error codes will be read by receiver.

Hardware flow control

Both sides with any communication protocol will be allocated with buffer of limited storage space to receive the data from other side. Once the other party sends data too fast, and processing speed of itself is slow, there may be a serious situation that the buffer is full and cannot be processed, and even data loss.

In this situation, the flow control is extremely important: When the receiver is unable to burden more date, it will notify the transmitter to stop sending data. After that, if it is capable to accept, it will notify transmitter again to transmit data.

See above diagram for UART interface of HW flow control pin. Compared with former, two pins namely RTS and CTS are added.

RTS

Output capability, which connects to the CTS of other side. When the RTS of its is pulled high, it will notify the UART of other side to stop transmitting data. Once the RTS goes back to low, it will notify the other side to transmit data again.

CTS

Input capability, which connects to the RTS of other party. When the CTS of its own side detects the high, it will stop transmitting data. Once the low level is detected by CTS of its, it is valid to transmit data.

FIFO

As one kind of basic data structures, the synchronous and asynchronous FIFO (First-In, First-Out) can be implemented in HW and SW. (In this chapter, it will introduce synchronous FIFO only)

Definition: The FIFO implemented by programming data structure in SW, like array and linked list.

• Application: Task scheduling in operation system, data packet processing in network or any scenario that needs queue.

• Operation: Enqueue (add to the back of the queue) and dequeue (remove from the front of the queue)

• Advantage: Flexible, which can adjust the size or implement priority queue easily.

• Disadvantage: Since it is implemented in SW, it will not as fast as HW FIFO.

As for SW FIFO, the ringbuffer is widely used.

Compared with linear buffer, there is no need to allocate memory frequently. The repeated usage in memory will allow us to carry out more tasks with fewer memory blocks. Meanwhile, it will be more convenient and safer to manage memory. Normally, the ringbuffer will be used when reading and writing buffer frequently.

ringbuff

The ringbuffer refers to buffer made by a logic ring with head and tail connected instead of that in physical. Since the memory space is made by linear structure, the ringbuffer is still one section of memory with certain length of FIFO actually. Moreover, it has the function of mutually exclusive access of communication processes to the buffer.

Principle

The ringbuffer is endowed with fixed length, as a result, it just needs to adjust the location of head, write pointer and tail pointer that point at this buffer instead of deleting all data when deploying it. The write pointer will point at head pointer first of all (The start location of ringbuffer) and the data will be saved in write pointer. In addition, the location of write pointer will move back for one certain length when one data is stored each time. Once the write pointer points at the tail pointer, it will re-point at head pointer and cover the original location till all data is stored. The benefit of ringbuffer lies in that it will reduce memory allocation, decrease system cost and memory fragment quantity, facilitating long and stable running.

UART-Communication

Generally, one ringbuffer is composed by one consecutive memory space and 4 pointers.

head Pointer: Point to the start address of memory tail Pointer: Point to the end address of memory read pointer: Point at the start location where stores data in memory write pointer: Point at the end location where stores data in memory

After applying for memory and pointer definition, see following content on ringbuffer illustration and application.

• This memory length will be displayed as: Len = tail-head

• The read pointer refers to the start location of reading data. After reading N data, it is needed to move offset with N length. Also, it is necessary to store the data with addlen into ringbuffer. If it meets addlen + write pointer > tail, the write pointer will store data with len1 = tail - write pointer and go back to head. The remaining data with len2 = addlen - len1 will be stored from head and overwrite the former data.

• The write pointer refers to the start location of writing data. After storing N data, it is needed to move offset with N length. When it is needed to read data with addlen from ringbuffer, if it meets addlen + read pointer > tail, the read pointer will store data with len1 = tail - read pointer and go back to head. The remaining data with len2 = addlen - len1 will be read from head till the end.

HW FIFO

• Definition: The FIFO implemented in HW, especially in digital circuit

• Application: Commonly used in communication interface such as UART and SPI for data buffer.

• Implementation: It will be implemented via register array or RAM with dual-interface. Moreover, it is endowed with read pointer and write pointer.

• Advantage: Fast speed, which can operate with other HW modules at the same time. Moreover, it can provide efficient data flow.

• Disadvantage: Fixed size, which is not as flexible as SW FIFO

Currently, the HW FIFO is used by QuecPython Series for data buffer and cross-asynchronous data transmission based on HW circuit.

Synchronous FIFO

• Definition: The read and write of synchronous FIFO are operated in the same clock.

• Principle: The same clock signal will be used to control the data read and write. Once the new data is written, the write pointer will move; When the data is read, the read pointer will move as well.

• Application: Commonly used in data flow buffer in the same clock domain.

synchronous-fifo

Write: The FIFO can store or write data in each location of clock according to w_en signal till the data is full. Meanwhile, the write pointer will increment when each data is written into FIFO memory.

Read: It will extract or read data from FIFO in each location of clock according to rd_en signal till the data is empty. Meanwhile, the read pointer will increment when each data is read from FIFO memory.

The read and write pointers will be generated by counting write and read requests in inner FIFO, which indicate the read and write address of memory. To be specific, the write pointer will point at the next address to be written while the read pointer points at the next address to be read. Similarly, the write request will increment write pointer and the read request will increment read pointer.

The module with FIFO will output empty and full signal to indicate its state, which are displayed as fifo_full and fifo_empty. The “fifo_full” means the fifo memory is full and not allowed to write data. While the “fifo_empty” indicates that there is no next valid data could be read in memory.

Reason to generate fifo_full and fifi_empty in synchronous FIFO

When resetting, the read and write pointer in FIFO will turn to zero. In this situation, when pulling up the fifo_empty, it allows to write without reading, once the new data is written, the fifo_empty will be pulled down and allowed to read data. Under the circumstance that the write pointer of fifo points at fifi_depth-1, the write operation will make the write pointer turned to zero and pulled the fifo_full high.

When the write pointer is equivalent to read pointer, the fifo will be either full or empty. Therefore, it is needed to discriminate above two conditions.

1. FIFO_FULL

The FIFO_FULL is triggered by write: when the write facilitates the equivalence between read pointer and write pointer in next clock, the FIFO_full will occur. That is to say the write pointer catches up with read pointer with an assistance of write. That is, the write pointer is one circle behind the read pointer.

1. FIFO_EMPTY

The FIFO_empty is triggered by read: when the read facilitates the equivalence between read pointer and write pointer in next clock, the FIFO_empty will occur. That is to say the read pointer catches up with write pointer with an assistance of read.

FIFO Asynchronous FIFO

• Definition: The read and write of asynchronous FIFO will be operated in different clock domain.

• Working principle: Two independent clocks will be used to write and read respectively. However, it demands special design to ensure the intactness and synchronization of data that crosses clock domain.

• Application: Data transmission of two clock domains with different operation frequency or different sources.

DMA

The DMA, acronym of Direct Memory Access, allows peripherals such as Hard disk, audio interface and network adaptor to exchange data with system memory without going through CPU. This mechanism can improve data transmission efficiency heavily since it allows device to transmit data without occupying CPU time.

Characteristics

The DMA and CPU are not parallel since there exists only one main memory. As a result, it is unavailable for both CPU and DMA to access main memory at the same time. The high efficiency lies in that the on-spot protection and recovery are not needed.

The DMA transmission itself will occupy system resource such as IO or RAM instead of interrupting program. Thus, once it is demanded for CPU to access to same IO or RAM, it will take extremely long time till the DMA transmission is done and the resource is released. From the perspective of SW, it is similar with interrupting program. However, the essence is quite different since the CPU works continuously without switching task. Finally, there is no need to protect on-spot.

Moreover, if the CPU owns certain cache and the DMA transmission speed is adequate, the SW will not detect that the program is halted even if the same RAM is accessed.

Operating process

1. Inquiry and Authorize：

– When a peripheral such as hard disk controller shall exchange data with memory, it will deliver one DMA request (DRQ as well) to DMA controller.

– Once the request is received by DMA controller, it will execute data transmission when the system bus is in idle state.

– Once prepared, the DMA controller will send a DMA Grant (DACK) to CPU, which will make the CPU paused after the current command is executed and release bus control.

1. Data transmission：

– The DMA controller will take charge bus and carry out data transmission. It can transmit in single byte or a patch of data in accordance with actual setting.

– The DMA controller will update source and target addresses and count the bytes that still need to be transmitted.

– In stage of data transmission, the CPU will be inactive or “isolated” since it does not take part in it.

1. Accomplished transmission：

– Once all data has been transmitted by DMA controller, it will delete DMA Grant signal.

– The DMA controller will transmit one interrupt signal (Under the circumstance that it has been set) to CPU to notify that the data transmission is accomplished. Therefore, the CPU can retrieve to process data or execute other tasks.

1. Interrupt service：

– If the interrupt that has been implemented in DMA is enabled, the CPU will receive one interrupt request after the data transmission is done.

– The CPU will call corresponding interrupt service routine (ISR) to process tasks after transmission such as post-data processing, error checking and so on.

1. Reset and prepare next DMA：

– The DMA controller will reset its state and prepare responding next DMA request.

Characteristic and Application

Characteristics

1. Simplicity: The HW and programming in UART communication will be simpler since the UART is implemented in micro-controller or other processor. Therefore, no extra chip is needed in terms of HW.

2. Unnecessary clock sync: Since the UART is async, there is no need to share the same clock signal when transmitting and receiving, reducing the complexity in HW design.

3. Flexibility: In UART communication, it is available to adjust data bit length, stop bit quantity and parity check according to various demands.

4. Reliability: Although it is not equipped with BF (Bug Fix) in UART, the Parity check is capable to detect error to some extent.

5. Limitation: To some extent, the UART communication speed is restricted. In addition, the faster communication speed, the more error will occur as well. Meanwhile, it is also demanded in distance. For long distance, the RS-422 and RS-485 will be used probably.

Application

1. Embedded system : The UART will be widely used in micro-controllers or other lower HW devices such as sensor, SD card and GPS module.

2. Serial communication : The UART can be applied to RS232, RS422 and RS485 to connect with printer, modem and display.

3. Computer HW: In preliminary computer HW, the UART will be used in interface of peripherals such as mouse and keyboard.

4. Telecommunication device: In wireless communication and telecommunication device, the UART will communicate with SIM card and other devices.

5. BT module: In BT module, the UART will communicate with host device.

6. IoT device: In IoT device, the UART will communicate among devices with low speed

Supported situation

For support of individual QuecPython module, see machine.UART

Data flow

It will introduce UART data flow based on QuecPython EC600U module

Data flow in Transmitting data

Under the circumstance that the data is invisible in FIFO more than 500ms, the data transmission will be ended.

TX communication: Transmit data -Transmit event once data transmission is complete-trigger interrupt-trigger callback function and transmit event to corresponding thread and process- corresponding thread triggers callback function defined by user.

Only one type can trigger interrupt: TX_COMPLETE.

Flow in receiving data

In terms of RX communication, there exist two interrupts -dma (64 bytes are received) OT (In condition that less than 64 bytes are received without triggering dma interrupt for 40ms)

Two kinds will trigger interrupt: RX_ARRIVED and RX_OVERFLOW

In condition that the SW FIFO is full, issues such as data overflow and data loss will occur if it receives more data. Meanwhile, the RX_OVERFLOW event will be reported. Therefore, it is necessary to process the received data, otherwise, it will occur issue such as data loss and incomplete data. For data transmission with large quantity, the HW flow control can be considered.

Rx communication: Receive data for 64 bytes or OT -> trigger interrupt-> trigger callback function and send event to corresponding thread and process-> corresponding thread triggers callback function defined by user.

Applications

Basic Tx/Rx

In terms of communication module, one simplified method is provided by QuecPython to carry out UART communication. For real-time application or scenario needs deal with UART info effectively, it is suggested to read UART via callback function.

Before that, it is necessary to learn about UART QuecPython Interface, see machine.UART

Procedure:

1. Initialize UART

from machine import UART # Initialize UART1 uart1 = UART(UART.UART1, 115200, 8, 0, 1, 0)

1. Write into UART Transmit data to UART

uart1.write('Hello UART1')

1. Read data via callback function

When deploying callback function in UART, one IRQ (Interrupt request) will be set to monitor UART event such as data reception. Under the circumstance that these events are triggered, relevant callback function will be executed.

Please make sure the callback function should be as short as possible so as to reduce the interference to other system tasks. Meanwhile, it is a must to read data immediately when arrival to avoid data loss owing to FIFO overflow underlying.

def uart_callback(arg):

_queue.put(para[2])

Set interrupt

uart1.setcallback(uart_callback)

Example:

Common issues and errors

As a simple and direct communication protocol, it may occur various issues in actual scenario for UART. See following common issues and investigation.

1. Receive data improperly or fails to receive data

It might be originated from several reasons, including wrong baud-rate, HW connection, interrupt processing and buffer overflow. See next investigation steps.

• Check whether the baud-rate in Tx and Rx is aligned. If it isn’t, which may cause error in receiving data.

• Check HW connection: please make sure the proper connection in Tx, Rx and GND lines.

• If interrupt processing is used, please guarantee that it can process the received data properly and retain all data.

• Check Rx buffer. The unduly small space or slow race in processing will lead to data loss. Thus, it is suggested to enlarge buffer size or optimize processing.

1. Send data incorrectly or fails to send data

It might be originated from several reasons, including HW connection, Tx buffer and Tx program. See next investigation steps.

• Check HW connection: please make sure the proper connection in Tx, Rx and GND lines.

• Check Tx buffer and Tx program: please make sure the data to be transmitted will be placed into buffer properly. While the Tx program can read data from the buffer and transmit properly.

1. Communication distance

The communication distance on UART is restricted: unduly long communication distance may lead to signal attenuation, influencing data reception. If it is needed to communicate via longer distance, differential signal standard such as RS-422 or RS-485 shall be deployed.

1. Interference

In EMI environment, the UART communication may be influenced heavily. If possible, try reduce EMI via shielding wire or reduce noise and EMI via capacitance filter. If extremely huge interference, the differential signal standard or optoelectronic isolator shall be used instead.

When investigating error, it is available to observe UART signal via logic analyzer or oscillator, which can do a favor in tracing issue. While in SW, it is available to observe and analyze the running state of program via corresponding debugging tool.